The present invention herein relates generally to semiconductor memory devices, and more particularly to a semiconductor memory device capable of executing a wear leveling method.
Semiconductor memory devices are used to store data, and may be generally categorized as volatile and nonvolatile in their operation. Data stored in a volatile memory device is lost when applied power is interrupted, while data stored in a nonvolatile memory device is retained even in the absence of applied power. As a result, nonvolatile memory devices are commonly employed in portable consumer electronics as mobile storage units.
Flash memory is a popular type of nonvolatile memory. Flash memory may be efficiently erased on a block-by-block basis before a programming operation, as compared with generic disk drive devices operating in an erase-before-program mode.
Since the data stored in flash memory cannot be directly updated, an erase operation is required before programming data. The required block-by-block erase operations inevitably “wear” (i.e., adversely effects the long term data storage capabilities of) the flash memory. Some form of wear leveling is required to ensure that certain memory blocks are not overly worn by repeated erase operations relative to other memory blocks.
The capacity of a particular flash memory device to withstand wear is referred to as “endurance”. Endurance is often expressed as a maximum number of erase operation cycles that may be applied before adverse wear effects the normal operation of the memory. Endurance varies between different types of nonvolatile memory devices. For example, flash memory generally has an endurance property in the range of tens to hundred of thousands of erase operation cycles.
An active memory management scheme is required to manage wear across a plurality of available memory blocks in order level (e.g., operationally equalize) wear effects and maximize the useful life of the memory. However, conventional wear management routines result in significant additional overhead to the operation of a semiconductor memory device. Further, many conventional wear management routines operate without any direct relation to actual input/output (I/O) operations. Such routines may degrade memory performance and fail to adequately manage actual wear.